Looks like AEHR’s chart bottomed out at the end of last week at a recent low of $.80. We would not be surprised to see AEHR break out above the 50 day moving average at around $.90. Technical indicators are bullish right now for AEHR.
Company Overview
Headquartered in Fremont, California, Aehr Test Systems is a leading worldwide provider of systems for burning-in and testing DRAMs, flash, and other memory and logic integrated circuits and has an installed base of more than 2,500 systems worldwide. Aehr Test has developed and introduced several innovative products, including the ABTS, FOX(TM), MTX and MAX systems and the DiePak(R) carrier. The ABTS is Aehr Test's newest system for packaged part test during burn-in for both low-power and high-power logic as well as all common types of memory devices. The FOX system is a full wafer contact test and burn-in system. The MTX system is a massively parallel test system designed to reduce the cost of memory testing by performing both test and burn-in on thousands of devices simultaneously. The MAX system can effectively burn-in and functionally test complex devices, such as digital signal processors, microprocessors, microcontrollers and systems-on-a-chip. The DiePak carrier is a reusable, temporary package that enables IC manufacturers to perform cost-effective final test and burn-in of bare die.
What is Burn In?
Burn-in is the process of stressing and exercising electrical devices to ensure optimum performance. This process forces defective semiconductor devices to fail before they are incorporated into assemblies where they can cause reliability problems in the end product.
Test & Reliability Screening Process
Burn-in can be done in different product development stages: engineering (design, reliability, or quality), and production. It can be performed on a small sample of devices, or all devices. You can burn-in unpackaged devices, packaged devices or devices mounted on PC boards. The most common method is to burn-in devices in production after packaging and before final test.
Static or Dynamic?
When you burn-in IC devices, you electrically stress or "exercise" the device and apply hot or cold temperatures in a thermal chamber for an extended period of time. If the DUT (Device Under Test) is biased, but is not being exercised electrically, the burn-in is referred to as Static Burn-in. If the DUT is exercised, the burn-in is referred to as Dynamic Burn-in. The exercise can be dynamic activity (clock signals of various frequencies) or functional exercise (signals that simulate actual use). Functional signals exercise more of the internal nodes of the device and are considered to be a superior method for detecting defective devices. Dynamic burn-in is the most common method used today.
What is Test During Burn-in (TDBI)?
TDBI applies functional input patterns and monitors the outputs of the DUTs for correct functional response. This method identifies the precise time and conditions of any failures. Generally, TDBI systems are more costly and demand more programming time. TDBI signal timing must be precise and monitoring strobes must be carefully placed to capture the response.
What is Parallel Functional Test?
Traditional Process Flow
Price competition is a major concern for most semiconductor memory manufacturers. In the last few years, memory prices have declined dramatically, forcing manufacturers to work aggressively to reduce production costs. As memories grow in size and complexity, test time increases geometrically. As a result, testing accounts for an increasing share of the cost of memory production.
Dataquest has estimated that final test costs represent 8.5 percent of the total manufacturing cost of DRAMs. Much of this cost is directly attributable to the way memories are tested. Memory manufacturers normally rely on a multi-phase testing process in which each device is burned-in and tested to ensure that it meets the performance and reliability specifications required. During burn-in, memories are electrically and thermally stressed, typically for several hours, to accelerate failures so they can be detected during final test. This process allows manufacturers to screen out defective ICs, including those with latent defects, prior to shipment and incorporation into end products.
Final testing is traditionally performed using very expensive, high performance multi-site testing equipment. This equipment, which can cost more than $2.5 million per system, is only capable of testing up to 64 ICs at a time. Unfortunately, since only a fraction of the tests performed by these systems actually require the costly high performance features, the tester's capabilities are severely underutilized.
Massively Parallel Test Systems perform the time consuming functional tests of the traditional tester, off-loading up to 80 percent of the test time from the final tester. Massively Parallel Test Systems, such as the MTX Parallel Functional Test System, are a cost-effective solution that can test thousands of ICs simultaneously and can provide traditional burn-in as well. This allows semiconductor manufacturers to use their higher cost testers for the high speed and high accuracy tests for which they are best suited, rather than inefficiently using them for time-consuming functional tests. Using the massively parallel memory testing solution rather than traditional testing methods, high volume memory manufacturers can reduce their equipment expenditures by tens of millions of dollars.
Because it combines burn-in and functional tests, there are no additional handling steps required to realize the benefits of a massively parallel test system. Moreover, testing during burn-in detects intermittent failures that only occur during burn-in and that would otherwise pass during a traditional final test. Test results from high-accuracy massively parallel test systems correlate extremely well with those obtained using traditional memory testers.
What is Die-Level Burn-in and Test?
IC manufacturers are creating more expensive package designs and multi-chip module (MCM) packages to deliver increased packaging density. MCMs contain several individual die in each package. Presently, burn-in and test are performed after the die are assembled into the module. Manufacturers realize that repairing or discarding a defective MCM is far too costly. As a result, die level burn-in and test of the individual die (before packaging) ensures that they only package known-good die (KGD) and, in turn, produce a quality product at a reduced cost.
Management
Rhea Posedel CHAIRMAN OF THE BOARD AND CEO
Founder of the Company and has served as Chief Executive Officer and Chairman of the Board of Directors since its inception in 1977. From the Company's inception through May 2000, Mr. Posedel also served as President. Prior to founding the Company, Mr. Posedel held various project engineering and engineering managerial positions at Lockheed Martin Corporation (formerly "Lockheed Missile & Space Corporation"), Ampex Corporation, and Cohu, Inc. He received a B.S. in Electrical Engineering from the University of California, Berkeley, an M.S. in Electrical Engineering from San Jose State University and an M.B.A. from Golden Gate University.
Gary L. Larson VP OF FINANCE AND CFO
Joined the Company in April 1991 as Chief Financial Officer and was elected Vice President of Finance in February 1992. From 1986 to 1990, he served as Chief Financial Officer, and from 1988 to 1990 also as President and Chief Operating Officer, of Nanometrics Incorporated, a manufacturer of measurement and inspection equipment for the semiconductor industry. Mr. Larson received a B.S. in Mathematics/Finance from Harvey Mudd College.
Carl N. Buck VP OF MARKETING AND CONTACTOR BUSINESS GROUP
Joined the Company as a Product Marketing Manager in 1983 and held various positions until he was elected Vice President of Engineering in November 1992, VP of Research and Development Engineering in November 1996, VP of Marketin g in September 1997, VP of Contactor Business Group in May 2002 and VP of Marketing and Contactor and Business Group in October 2005. From 1978 to 1983, Mr. Buck served as Product Marketing Manager at Intel Corporation, an integrated circuit and microprocessor company. Mr. Buck received a B.S.E.E. from Princeton University, an M.S. in Electrical Engineering from the University of Maryland and an M.B.A. from Stanford University.
Joel Bustos VP OF OPERATIONS
Joined the Company as Vice President of Operations in July 2007. From 2002 to 2007, Mr. Bustos served as General Manager of the Global Consumer Business Unit of Celestica Inc., an electronic manufacturing services company. From 1999 to 2002, Mr. Bustos served as a General Manager at Flextronics International Ltd., a leading global provider of electronic manufacturing services. Mr. Bustos received a B.S. in Organizational Behavior from the University of San Francisco.
David S. Hendrickson VP OF ENGINEERING
Joined the Company as Vice President of Engineering in October 2000. From 1999 to 2000, Mr. Hendrickson served as Platform General Manager, and from 1995 to 1999 as Engineering Director and Software Director, of Siemens Medical (formerly Acuson Corporation), a medical ultrasound products company. From 1990 to 1995, Mr. Hendrickson served as Director of Engineering and Director of Software of Teradyne Inc. (formerly Megatest Corporation), a manufacturer of semiconductor capital equipment. Mr. Hendrickson received a B.S. in Computer Science from Illinois Institute of Technology.
Gregory M. PerkinsVP OF WORLDWIDE SALES AND SERVICE
Joined the Company as Vice President of Worldwide Sales and Service in June 2004. From 2001 to 2003, Mr. Perkins served as Vice President of North America Customer Operations and then Vice President of North American and European Sales, for Electroglas Corporation, a producer of semiconductor wafer probers. From 1999 to 2001, he served as Vice President to Sales at Advantest America, Inc., a semiconductor tester company, and from 1997 to 1999 as Vice President of Worldwide Sales and Field Operations at LTX Corporation, a semiconductor tester company. From 1978 to 1997, Mr. Perkins held multiple management positions over 19 years with General Electric Company including Senior Vice President of Marketing and Business Development for GE Capital Computer Leasing. Mr. Perkins received a B.S. degree in Environmental Health Technologies from Quinnipiac University.
Kunio Sano PRESIDENT, AEHR TEST SYSTEMS JAPAN K.K.
Joined the Company as Vice President, Aehr Test Systems Japan K.K., the Company's subsidiary in Japan, in June 1998 and was elected President, Aehr Test Systems Japan K.K. in January 2001. From 1991 to 1998, he served as Manager of Development Engineering Department at Tokyo Electron Yamanashi Limited, a leading worldwide semiconductor equipment manufacturer. Mr. Sano received a B.S.E.E. from Sagami Institute of Technology in Kanagawa, Japan.
BOARD OF DIRECTORS
ROBERT R. ANDERSON, Director, was appointed to the Company's Board of Directors in October 2000. Mr. Anderson has served as a director of Aviza Technology, Inc., a semiconductor equipment company, since December 2005. Mr. Anderson served on the Trikon board from April 2000 through the date of acquisition by Aviza. Mr. Anderson is a private investor. In addition, Mr. Anderson currently is a director of MKS Instruments, Inc., a semiconductor components and equipment supplier. He also serves as a director for one private company.
WILLIAM W. R. ELDER, Director, has been a director of the Company since 1989. Dr. Elder was the Chief Executive Officer of Genus, Inc. a semiconductor equipment company, from 1981 to 1996, and then again from 1998 until the company was acquired by AIXTRON AG ("AIXTRON") in 2005. Dr. Elder retired from AIXTRON in December 2007. Dr. Elder is currently EVP, Global Operations and a Director of Maskless Lithography Inc., a capital equipment start-up company based in San Jose, California. Dr. Elder holds a B.S.I.E. and an honorary Doctorate Degree from the University of Paisley in Scotland.
MUKESH PATEL, Director, was appointed to the Company's Board of Directors in June 1999. Mr. Patel was President and Chief Executive Officer of Metta Technology, which he co-founded in 2004, until November 2006, when LSI Logic Corporation acquired it. He founded Sparkolor Corporation, acquired by Intel Corporation in late 2002, and co-founded SMART Modular Technologies, Inc. ("SMART Modular"), a high value added memory products company, acquired by Solectron Corporation in late 1999. Mr. Patel was Vice President and General Manager Memory Product Division of SMART Modular from August 1995 to August 1998 and was Vice President, Engineering from February 1989 to July 1995. Mr. Patel holds a B.S. degree in Engineering with an emphasis in digital electronics from Bombay University, India. Mr. Patel also serves as a director of SMART Modular and for several privately-held companies.
HOWARD T. SLAYEN, Director, has been providing independent financial consulting services to various organizations and clients since June 2001. From October 1999 to May 2001, Mr. Slayen was Executive Vice President and Chief Financial Officer of Quaartz Inc., a web-hosted communications business. From 1971 to September 1999, Mr. Slayen held various positions with PricewaterhouseCoopers/Coopers & Lybrand, including his last position as a Corporate Finance Partner. In addition, Mr. Slayen currently is a director of Lantronix, Inc., a provider of embedded networking solutions. He also serves as a director for two private companies. Mr. Slayen holds a B.A. from Claremont McKenna College and a J.D. from the University of California, Berkeley School of Law.
